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[VHDL-FPGA-Verilog] dfe_filter

Description: DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
Platform: | Size: 2048 | Author: 右下角 | Hits:

[VHDL-FPGA-Verilog] Ahb2Apb

Description: AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
Platform: | Size: 5120 | Author: local_boy | Hits:

[VHDL-FPGA-Verilog] UDP_verilog

Description: Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc.
Platform: | Size: 17010 | Author: sunhaichaook@163.com | Hits:

[VHDL-FPGA-Verilog] modelsim se 10.1a crack

Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.)
Platform: | Size: 523264 | Author: 冰激凌很牛 | Hits:

[VHDL-FPGA-Verilog] sdr_sdram

Description: sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
Platform: | Size: 12288 | Author: 风雪来 | Hits:

[Other] 高大上欧美风商务PPT模板

Description: JPEG_d IP Core Verilog crypted source
Platform: | Size: 15606784 | Author: 发企鹅出去啊 | Hits:

[VHDL-FPGA-Verilog] 8051Core

Description: 8051 Core Verilog RTL IP Code
Platform: | Size: 1597440 | Author: richman | Hits:
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